1. Field of the Invention
The present invention relates to an active bias circuit and more particularly, to an active bias circuit with a combined configuration of the Wilson configuration for current source and the Widlar configuration for current source.
2. Description of the Related Art
FIG. 1 shows a conventional active bias circuit 10 having a combined configuration of the Wilson and Widlar current source configurations. As shown in FIG. 1, this bias circuit 10 comprises four n-channel Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) M11, M12, M13, and M14 and a resistor R11.
Each of the MOSFETs M11 and M14 has a so-called diode connection. Thus, the gate and the drain of the MOSFET 11 are coupled together at the point P1 and the gate and the drain of the MOSFET 14 are coupled together at the point P2. The drain of the MOSFET M11 is connected to the terminal T1 by way of the resistor R11 while the gate of the MOSFET M11 is connected to the gate of the MOSFET M13. The source of the MOSFET M11 is connected to the drain of the MOSFET M12. The gate and the source of the MOSFET M12 are connected to the gate and the source of the MOSFET M14, respectively. The coupled sources of the MOSFETs M12 and M14 are connected to the ground. Thus, the MOSFETs M11 and M12 located at the input side are connected in cascode.
The drain and the source of the MOSFET M13 are connected to the terminal T2 and the drain of the MOSFET M14, respectively. The output terminal T3 of the active bias circuit 10 is connected to the point P2 at which the gate and the drain of the MOSFET M14 are coupled together. Thus, the MOSFETs M13 and M14 located at the output side also are connected in cascode.
A reference voltage V1 is applied to the terminal T1, thereby generating a reference current IREF flowing through the resistor R11. In other words, the reference current IREF is generated by the reference voltage V1 and the resistor R11. Since it can be considered that no gate current flows to the gates of the MOSFETs M11 and M13, the reference current IREF is equal to the drain current ID11 of the MOSFET M11 and to the drain current ID12 of the MOSFET M12 (i.e., IREF=ID11=ID12).
A bias voltage V2 is applied to the terminal T2, thereby generating the drain current ID13 of the MOSFET M13. The value of the drain current ID13 has a specific ratio with respect to that of the reference current IREF. Specifically, the value of the drain current ID13 is a times as much as that of the reference current IREF, where a is a positive constant (i.e., ID13=aIREF). Since it can be considered that no gate current flows to the gates of the MESFETs M12 and M14, the drain current ID13 is equal to the drain current ID14 of the MOSFET M14 (i.e., ID13=ID14).
The output bias voltage VOUT of the conventional bias circuit 10 is generated at the output terminal T3. The output bias voltage VOUT is equal to the voltage at the connection point P2 of the gate and the drain of the MOSFET M14 (i.e., the connection point of the drain of the MOSFET M14 and the source of the MOSFET M13).
A target circuit 20, to which the output bias voltage VOUT is applied from the active bias circuit 10, includes an n-channel enhancement MOSFET M15. The gate of the MOSFET M15 is connected to the output terminal T3 of the circuit 10, receiving the bias voltage VOUT of the circuit 10. The drain of the MOSFET M15 is connected to the terminal T4 to which a voltage VD is applied. The source of the MOSFET M15 is connected to the ground.
Although the target circuit 20 includes other active elements and other passive elements along with the MOSFET M15, they are omitted in FIG. 1 for the sake of simplification.
The conventional active bias circuit 10 of FIG. 1 operates in the following way.
If the value of the reference resistor R11 is suitably determined or adjusted according to the value of the reference voltage V1 (e.g., 2V), the value of the reference current IREF flowing through the MOSFET M11 can be set as desired. Also, due to the reference current IREF thus set, the value of the voltage VP1 at the connection point P1 (i.e., the connection point of the resistor R11 and the drain of the MOSFET M11) is determined. In this case, the value of the voltage VP2 at the connection point P2 (i.e., the output terminal T3) is given as the difference of the forward voltage drop VFM13 of the MOSFET M13 from the value of the bias voltage V2 applied to the terminal T2. Thus, the following equation (1) is established.
VP2=VOUT=V2xe2x88x92VFM13xe2x80x83xe2x80x83(1)
Thus, when the value of the reference voltage VREF applied to the terminal T1 (i.e., the reference current IREF) is changed, the values of the drain current ID13 of the MOSFET M13 and the forward voltage drop VFM13 thereof are changed, resulting in change of the output bias voltage VOUT. This means that even if the bias voltage V2 is not changed, the output bias voltage VOUT can be changed by changing the reference voltage V1.
The value of the drain current ID15 of the MOSFET M15 varies according to the value of the output bias voltage VOUT applied to the gate of the MOSFET M15 in the target circuit 20. Since the MOSFET M15 is of the enhancement type, the value of the drain current ID15 of the MOSFET M15 can be set as zero (0V) if the value of the output bias voltage VOUT is set to be equal to or lower than the threshold voltage of the MOSFET M15. Thus, the MOSFET M15 can be cut off.
The operation of the bias circuit 10 shown in FIG. 1 scarcely fluctuates even if the threshold voltages Vth of the MOSFETS M11, M12, M13, and M14 fluctuate due to change of the various parameters in their fabrication process sequence and/or the ambient temperature of the circuit 10 varies during operation. In other words, as long as the parameters of the circuit 10 are kept unchanged, the value of the drain current ID15 of the MOSFET M15 in the target circuit 20 is kept approximately constant in spite of the fluctuation of the threshold voltage and the ambient temperature.
For example, when the absolute value (i.e., amplitude) of the threshold voltages Vth of the MOSFETs M11, M12, M13, and M14 decreases, the value of the reference current IREF increases according to the decrease of the threshold voltages Vth, lowering the voltage VP1 at the point P1. On the other hand, according to the increase of the reference current IREF, the drain current ID13 of the MOSFET M13 increases, which increases the voltage drop generated by the MOSFET M13. As a result, the value of the voltage VP2 at the point P2 (i.e., the output bias voltage VOUT) decreases.
On the contrary, when the absolute value (i.e., amplitude) of the threshold voltages Vth of the MOSFETs M11, M12, M13, and M14 increases, the value of the reference current IREF decreases according to the increase of the threshold voltages Vth, raising the voltage VP1 at the point P1. On the other hand, according to the decrease of the reference current IREF, the drain current ID13 of the MOSFET M13 decreases, which decreases the voltage drop generated by the MOSFET M13. As a result, the value of the voltage VP2 at the point P2 (i.e., the output bias voltage VOUT) increases.
With the conventional bias circuit 10, in the above-described manner, the drain currents ID13 and ID14 of the MOSFETs M13 and M14 (and therefore, the drain current ID15 of the MOSFET M15) are kept approximately constant against the fluctuation of the threshold voltages Vth.
The bias circuit 10 operates in the same way as above when the ambient temperature varies as well. Therefore, the drain current ID15 of the MOSFET M15 is kept approximately constant against the fluctuation of the ambient temperature.
However, the above-described conventional active bias circuit 10 has the following problems.
Specifically, with the conventional circuit 10, the power consumption of the target circuit 20 (i.e., the MOSFET M15) can be adjusted by changing the value of the reference voltage V1 applied to the terminal T1. This is due to the fact that the output bias voltage VOUT varies according to the change of the reference voltage V1, which changes the drain current ID15 of the MOSFET M15.
The bias circuit 10 is used, for example, for applying a desired bias voltage to an amplifier circuit provided in a mobile telephone. In this case, the target circuit 20 is the amplifier circuit.
With mobile telephones, generally, the voltage VD is supplied to the MOSFET M15 and at the same time, the output bias voltage VOUT with a desired value is supplied to the MOSFET M15 and the target circuit 20 (i.e., the amplifier circuit) by the bias circuit 10 in the normal operation. On the other hand, in the power-saving operation, the supply of the voltage VD to the MOSFET M15 is stopped with a switch (e.g., a so-called drain switch, not shown in FIG. 1) to stop temporarily the operation of the MOSFET M15 (and the circuit 20).
Thus, there is a problem that the count (i.e., total number) of the necessary parts increases because the drain switch is essentially provided. Also, there is another problem that the lifetime of the battery is shortened because the operation of the drain switch consumes some electric power.
If the drain switch can be eliminated, these two problems are easily solved. This is realized by, for example, setting the output bias voltage VOUT of the bias circuit 10 to be lower than the threshold voltage of the MOSFET M15, thereby stopping the operation of the MOSFET 15 and the target circuit 20. However, some mobile telephones have a configuration that does not permit the reference voltage V1 of 0 V. In this case, it is unable to set the output bias voltage VOUT of the circuit 10 to be lower than the threshold voltage of the MOSFET M15, making the MOSFET M15 cut off.
Moreover, with the conventional bias circuit 10, the output bias voltage VOUT is unable to be sufficiently low. As a result, it is impossible or difficult for the MOSFET M15 to consume less electric power as desired when the MOSFET M15 is operated at a low supply voltage. In other words, there is a problem that the variable range of power consumption of the MOSFET M15 by the reference voltage V1 is narrow.
In addition, the Japanese Non-Examined Patent Publication Nos. 61-292405 published in 1986, 5-276015 published in 1993, 6-244659 published in 1994, and 4-61524 published in 1992 disclose the techniques that the voltage level is changed with the use of a diode or diodes. However, these techniques have no relationship with the active bias circuit of the type with a combined configuration of the Wilson and Widlar current source configurations.
Accordingly, an object of the present invention is to provide an active bias circuit that expands the variable range of power consumption of a target circuit that varies by changing the value of a reference voltage.
Another object of the present invention is to provide an active bias circuit that makes it possible to cut off a current flowing in a target circuit including an enhancement active element or device.
The above objects together with others not specifically mentioned will become clear to those skilled in the art from the following description.
An active bias circuit according to the present invention comprises:
(a) a first transistor with a diode connection;
the first transistor being supplied with a reference current by way of a resistor;
the first transistor having a control terminal;
(b) a second transistor connected in cascode to the first transistor;
the second transistor having a control terminal;
(c) a third transistor having a control terminal connected to the control terminal of the first transistor;
a constant current with a specific ratio with respect to the reference current flowing through the third transistor;
(d) a fourth transistor with a diode connection;
the fourth transistor being connected in cascode to the third transistor;
the fourth transistor having a control terminal connected to the control terminal of the second transistor;
(e) an output terminal formed between the third and fourth transistors connected in cascode;
an output bias voltage being derived from the output terminal;
the output bias voltage varying according to a reference voltage applied across the first and second transistors connected in cascode; and
(f) a diode with a specific forward voltage drop generated by a current flowing through the diode itself;
an absolute value of the output bias voltage being decreased by a value of the forward voltage drop of the diode.
With the active bias circuit according to the present invention, the diode with a specific forward voltage drop is provided. Utilizing the forward voltage drop of the diode, the absolute value of the output bias voltage is decreased by the value of the forward voltage drop. Thus, the current flowing through a target circuit to be supplied with the bias voltage from the active bias circuit can be cut off without any dedicated switch for current cut-off.
Also, the absolute value of the output bias voltage is smaller than that of the bias voltage applied across the third and fourth transistors connected in cascode by the value of the forward voltage drop of the diode. Therefore, the variable range of power consumption of a target circuit that varies by changing the value of the reference voltage can be expanded toward the low-value side.
In a preferred embodiment of the invention, the diode is connected between the third transistor and the output terminal in such a way that a forward direction of the diode and a direction of the constant current flowing through the third transistor are the same.
In another preferred embodiment of the invention, the diode is connected to the output terminal and a connection point of the third transistor and the fourth transistor, thereby decreasing the absolute value of the output bias voltage by the value of the forward voltage drop of the diode.
In still another preferred embodiment of the invention, one of an anode and a cathode of the diode is connected to the connection point of the first transistor and the other thereof is connected to the connection point of the second transistor, thereby decreasing the absolute value of the output bias voltage by the value of the forward voltage drop of the diode.
In a still further preferred embodiment of the invention, the active bias circuit is so designed that the output bias voltage is applied to a control terminal of a voltage-driven active element operable in an enhanced mode provided in a target circuit.